SH7018 Datasheet, PDF (139/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.4 Operation
8.4.1 Overview
The operation modes are described below.
Ordinary Operation: Each channel has a timer counter (TCNT) and general register (TGR). The
TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external
event counter. General registers (TGR) can be used as output compare registers or input capture
registers.
Synchronized Operation: The TCNT of a channel set for synchronized operation does a
synchronized preset. When any TCNT of a channel operating in the synchronized mode is
rewritten, the TCNTs of other channels are simultaneously rewritten as well. The timer
synchronization bits of the TSYR registers of multiple channels set for synchronous operation can
be set to clear the TCNTs simultaneously.
Buffer Operation: When TGR is an output compare register, the buffer register value of the
corresponding channel is transferred to the TGR when a compare-match occurs. When TGR is an
input capture register, the TCNT counter value is transferred to the TGR when an input capture
occur simultaneously the value previously stored in the TGR is transferred to the buffer register.
Cascade Connection Operation: The channel 1 and channel 2 counters (TCNT1 and TCNT2)
can be connected together to operate as a 32-bit counter.
PWM Mode: In PWM mode, a PWM waveform is output. The output level can be set by the
TIOR register. Each TGR can be set for PWM waveform output with a duty cycle between 0%
and 100%.
8.4.2 Basic Functions
Always select MTU external pin set function using the pin function controller (PFC).
Counter Operation: When a start bit (CST0 to CST2) in the timer start register (TSTR) is set to
1, the corresponding timer counter (TCNT) starts counting. There are two counting modes: a free-
running mode and a periodic mode.
To select the counting operation (figure 8.6):
1. Set bits TPSC2 to TPSC0 in the TCR to select the counter clock. At the same time, set bits
CKEG1 and CKEG0 in the TCR to select the desired edge of the input clock.
2. To operate as a periodic counter, set the CCLR2 to CCLR0 bits in the TCR to select TGR as a
clearing source for the TCNT.
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