SH7018 Datasheet, PDF (70/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 5.8 Interrupt Priority Order
Type
NMI
IRQ
Priority Level
16
0 to 15
On-chip peripheral module 0 to 15
Comment
Fixed priority level. Cannot be masked.
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
Set with interrupt priority level setting registers A
through H (IPRA to IPRH).
5.4.2 Interrupt Exception Processing
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.4, Interrupt Operation, for more information on the interrupt
exception processing.
5.5 Exceptions Triggered by Instructions
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal
slot instructions, as shown in table 5.9.
Table 5.9 Types of Exceptions Triggered by Instructions
Type
Source Instruction
Trap instructions TRAPA
Illegal slot
instructions
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
and instructions that rewrite the
PC
General illegal
instructions
Undefined code anywhere
besides in a delay slot
Comment
—
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
—
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