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SH7018 Datasheet, PDF (408/431 Pages) Renesas Technology Corp – SuperH™ RISC engine
Table 19.6 Bus Timing (cont)
Conditions: VCC = 3.0 to 3.6 V, PVCC = 5.0 ± 0.5 V, PVCC ≥ VCC, AVCC = 3.0 to 3.6 V,
AVCC ≥ VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = –20 to +75°C
Item
Symbol Min Max Unit Figure
Read data access time
t *1
ACC
tcyc × —
ns
Figure 19.6 to
(n*5 + 2)
figure 19.8
– 50
Access time from read strobe
t *1
OE
tcyc × —
ns
Figure 19.6 to
(n*5 +
figure 19.8
1.5) –
50
Write address setup time
t AS
0
—
ns
Figure 19.6 to
figure 19.8
Write address hold time
t WR
0
—
ns
Figure 19.6 to
figure 19.8
Write data hold time
t WRH
0
—
ns
Figure 19.6 to
figure 19.8
Notes: 1. The tRDS specification needs not be met as long as the access time specification is met.
2. tWDH (max) is a reference value.
3. The minimum (min) values for delay times are reference (typical) values.
4. tRDS is a reference value.
5. The n is the wait number.
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