SH7018 Datasheet, PDF (201/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
CMCNT
input clock
CMCNT
N
0
CMCOR
N
Compare
match signal
CMF
CMI
Figure 10.4 CMF Set Timing
10.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1. Figure
10.5 shows the timing when the CMF bit is cleared by the CPU.
CMCSR write cycle
T₁
T₂
CK
CMF
Figure 10.5 Timing of CMF Clear by the CPU
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