SH7018 Datasheet, PDF (319/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

15.2.2 Port A Data Register L (PADRL)
Port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. The
bits of this register correspond to the various pins.
When a pin functions as a general output, if a value is written to PADRL, that value is output
directly from the pin, and if PADRL is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PADRL is read the pin state, not the register value, is
returned directly. If a value is written to PADRL, that value is written to PADRL but it does not
affect the pin state. Table 15.2 summarizes the port A data register read/write operations.
PADRL is initialized by an external power-on reset. However, it is not initialized by a WDT reset,
in standby mode, or in sleep mode.
Bit: 15
14
13
12
11
10
9
8
PA15DR PA14DR — PA12DR PA11DR PA10DR PA9DR PA8DR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Bit:
7
PA7DR
Initial value:
0
R/W: R/W
6
PA6DR
0
R/W
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
Table 15.2 Port A Data Register (PADR) Read/Write Operations
PAIOR
0
1
Pin Function
General input
Other than general input
General output
Other than general output
Read
Write
Pin state
Value is written to PADR, but does not affect
pin state
Pin state
Value is written to PADR, but does not affect
pin state
PADR value Write value is output from pin
PADR value Value is written to PADR, but does not affect
pin state
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