SH7018 Datasheet, PDF (131/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt TGFD requests when
the TGFD bit of the channel 0 of the TSR register is set to 0.
This bit is reserved for channels 1 and 2. It is always read as 0. The write value should always
be 0.
Bit 3: TGIED
0
1
Description
Disable interrupt requests (TGID) due to the TGFD bit
Enable interrupt requests (TGID) due to the TGFD bit
(Initial value)
• Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables TGFC interrupt requests when
the TGFC bit of the Channel 0 of the TSR register is set to 1.
This bit is reserved for channels 1 and 2. It is always read as 0. The write value should always
be 0.
Bit 2: TGIEC
0
1
Description
Disable interrupt requests (TGIC) due to the TGFC bit
Enable interrupt requests (TGIC) due to the TGFC bit
(Initial value)
• Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables TGFB interrupt requests when
the TGFB bit of the TSR register is set to 1.
Bit 1: TGIEB
0
1
Description
Disable interrupt requests (TGIB) due to the TGFB bit
Enable interrupt requests (TGIB) due to the TGFB bit
(Initial value)
• Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables TGFA interrupt requests when
the TGFA bit of the TSR register is set to 1.
Bit 0: TGIEA
0
1
Description
Disable interrupt requests (TGIA) due to the TGFA bit
Enable interrupt requests (TGIA) due to the TGFA bit
(Initial value)
115