SH7018 Datasheet, PDF (67/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

5.2 Resets
5.2.1 Reset
A reset has the highest priority of any exception source. As shown in table 5.5, a power-on reset
initializes the internal state of the CPU and the on-chip peripheral module registers.
Table 5.5 Types of Resets
Type
Power-on reset
Conditions for Transition
to Reset Status
RES
Low
CPU
Initialized
Internal Status
On-Chip Peripheral Module
Initialized
5.2.2 Power-On Reset
When the RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES
pin should be kept at low for at least the duration of the oscillation settling time when applying
power or when in standby mode (when the clock circuit is halted) or at least 20 t_cyc (when the
clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip
peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins
during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (1111).
4. The values fetched from the exception processing vector table are set in the program counter
(PC) and SP and the program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
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