SH7018 Datasheet, PDF (374/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

H'000000
Flash memory
EB0 to EB3
H'004000
H'0043FF
H'005000
H'0053FF
H'006000
H'0063FF
H'007000
H'0073FF
H'008000
EB4
EB5
EB6
EB7
(1 kB)
(3 kB)
(1 kB)
(3 kB)
(1 kB)
(3 kB)
(1 kB)
(3 kB)
Flash memory
EB8 to EB10
This area can be accessed
from both the RAM area
and flash memory area
H'FFFFF800
H'FFFFFBFF
On-chip RAM
H'027FFF
Figure 16.16 Example of RAM Overlap Operation
Example in Which Flash Memory Block Area (EB4) is Overlapped
1. Set bits RAMS, RAM1, and RAM0 in RAMER to 1, 0, 0, to overlap part of RAM
(H'FFFFF800 to H'FFFFFBFF) onto the area (part of EB4: H'004000 to H'0043FF) for which
real-time programming is required.
2. Real-time programming is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB4).
Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks
regardless of the value of RAM1 and RAM0 (emulation protection). In this state,
setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a
transition to program mode or erase mode. When actually programming a flash
memory area, the RAMS bit should be cleared to 0.
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