SH7018 Datasheet, PDF (203/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T₂ state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 10.7 shows the timing.
CMCNT write cycle
T₁
T₂
CK
Address
CMCNT
Internal
write signal
Compare
match signal
CMCNT
N
M
CMCNT write data
Figure 10.7 CMCNT Word Write and Increment Contention
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