SH7018 Datasheet, PDF (172/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Contention between Overflow and Counter Clearing: If overflow and counter clearing occur
simultaneously, the TCFV flag in TSR is not set and TCNT clearing takes precedence.
Figure 8.47 shows the operation timing when a TGR compare-match is specified as the clearing
source, and H'FFFF is set in TGR.
ø
TCNT input
clock
TCNT
Counter clear
signal
H'FFFF
H'0000
TGF flag
TCFV flag
Disabled
Figure 8.47 Contention between Overflow and Counter Clearing
Contention between TCNT Write and Overflow: If there is an up-count in the T2 state of a
TCNT write cycle, and overflow occurs, the TCNT write takes precedence and the TCFV flag in
TSR is not set .
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