SH7018 Datasheet, PDF (225/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 3: MPIE
0
1
Description
Multiprocessor interrupts are disabled (normal receive operation)
(Initial value)
MPIE is cleared when the MPIE bit is cleared to 0, or the multiprocessor
bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled
Receive-data-full interrupt requests (RxI), receive-error interrupt
requests (ERI), and setting of the RDRF, FER, and ORER status flags
in the serial status register (SSR1) are disabled until data with the
multiprocessor bit set to 1 is received.
The SCI does not transfer receive data from the RSR1 to the RDR1,
does not detect receive errors, and does not set the RDRF, FER, and
ORER flags in the serial status register (SSR1). When it receives data
that includes MPB = 1, MPB is set to 1, and the SCI1 automatically
clears MPIE to 0, generates RxI and ERI interrupts (if the TIE and RIE
bits in the SCR1 are set to 1), and allows the FER and ORER bits to be
set.
• Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled*
(Initial value)
1
Transmit-end interrupt (TEI) requests are enabled.*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR1)
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
• Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI1 clock source
and enable or disable clock output from the SCK pin. Depending on the combination of CKE1
and CKE0, the SCK pin can be used for serial clock output, or serial clock input. Select the
SCK pin function by using the pin function controller (PFC).
The CKE0 setting is valid only in the asynchronous mode, and only when the SCI1 is
internally clocked (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or
when an external clock source is selected (CKE1 = 1). Select the SCI1 operating mode in the
serial mode register (SMR) before setting CKE1 and CKE0. For further details on selection of
the SCI1 clock source, see table 12.9 in section 12.3, Operation.
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