SH7018 Datasheet, PDF (151/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

TCNT1
Clock
TCNT1
TCNT2
Clock
TCNT2
TIOC1A,
TIOC2A
TGR1A
H'03A1
H'FFFF
H'03A2
H'0000
H'0001
H'03A2
TGR2A
H'0000
Figure 8.22 Cascade Connection Operation Example (Input Capture)
8.4.6 PWM Mode
PWM mode outputs the various PWM waveforms from output pins. Output levels of 0 output, 1
output, or toggle output can be selected as the output level for the compare-match of each TGR.
A period can be set for a register by using the TGR compare-match as a counter clear source. All
five channels can be independently set to PWM mode. Synchronous operation is also possible.
There are two PWM modes:
• PWM mode 1
Generates PWM output using the TGRA and TGRB registers, and TGRC and TGRD registers
as pairs. The initial output values are those established in the TGRA and TGRC registers.
When the values set in TGR registers being used as a pair are equal, output values will not
change even if a compare-match occurs.
A maximum of 4-phase PWM output is possible for PWM mode 1.
• PWM mode 2
Generates PWM output using one TGR register as a period register and another as a duty cycle
register. The output value of each pin upon a counter clear is the initial value established by the
TIOR register. When the values set in the period register and duty register are equal, output
values will not change even if a compare-match occurs.
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