SH7018 Datasheet, PDF (165/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
Counter
clear signal
TCNT
N
H'0000
Figure 8.39 TCNT Write and Clear Contention
Contention between TCNT Write and Increment: If a count-up signal is issued in the T₂ state
during the TCNT write cycle, TCNT write has priority, and the counter is not incremented (figure
8.40).
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 8.40 TCNT Write and Increment Contention
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