SH7018 Datasheet, PDF (93/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.1.3 Pin Configuration
Table 7.1 shows the bus state controller pin configuration.
Table 7.1 Pin Configuration
Pin Name
A21 to A0
D7 to D0
CS0 to CS3
RD
WRL
WAIT
I/O
Output
I/O
Output
Output
Output
Input
Function
Address output
8-bit data bus
Chip select
Strobe that indicates a read cycle for ordinary space/multiplex I/O
Strobe that indicates a write cycle
Wait state request signal
7.1.4 Register Configuration
The bus state controller has three registers. The functions of these registers include control of wait
states and interfaces with memories such as ROM and SRAM. The registers are summarized in
table 7.2.
Both registers are 16 bits in size, and are initialized by a power-on reset.
Table 7.2 Register Configuration
Name
Bus control register 1
Bus control register 2
Wait state control register 1
Abbr.
BCR1
BCR2
WCR1
R/W Initial Value Address Access Size
R/W H'200F
H'FFFF8620 8, 16
R/W H'FFFF
H'FFFF8622 8, 16
R/W H'FFFF
H'FFFF8624 8, 16
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