SH7018 Datasheet, PDF (346/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation
in RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 2:
RAMS
0
1
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
(Initial value)
• Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. For each block, only
the first 1 kB of addresses can be overlapped. (See table 16.4.)
Table 16.4 Flash Memory Area Divisions
Addresses
H'FFF800 to H'FFFBFF
H'004000 to H'0043FF
H'005000 to H'0053FF
H'006000 to H'0063FF
H'007000 to H'0073FF
Block Name
RAM area 1 kB
EB4 (1 kB)
EB5 (1 kB)
EB6 (1 kB)
EB7 (1 kB)
RAMS
0
1
1
1
1
RAM1
*
0
0
1
1
RAM0
*
0
1
0
1
16.6 On-Board Programming Modes
When pins are set to on-board programming mode and a power-on reset-start is executed, a
transition is made to the on-board programming state in which program/erase/verify operations
can be performed on the on-chip flash memory. There are two on-board programming modes: boot
mode and user program mode. The pin settings for transition to each of these modes are shown in
table 16.5. For a diagram of the transitions to the various flash memory modes, see figure 16.2.
Table 16.5 Setting On-Board Programming Modes
Mode
Boot mode
User program mode
FWP
0
0
MD3
0
0
MD2
0
0
MD1
0
1
MD0
0
0
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