SH7018 Datasheet, PDF (125/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Channel 0 (TIOR0L Register):
Bit 6: Bit 5: Bit 4:
IOD2 IOD1 IOD0 Description
0
0
0
TGR0D is an output Output disabled
(Initial value)
1
compare register
Initial
Output 0 on compare-match
1
0
1
output
is 0
Output 1 on compare-match
Toggle output on compare-match
1
0
0
Output disabled
1
1
0
1
Initial
output
is 1
Output 0 on compare-match
Output 1 on compare-match
Toggle output on compare-match
Bit 3: Bit 2: Bit 1: Bit 0:
IOC3 IOC2 IOC1 IOC0 Description
0
0
0
0
TGR0C
Output disabled
(Initial value)
1
is an
Initial
1
0
output
compare
output
is 0
1
register
Output 0 on compare-match
Output 1 on compare-match
Toggle output on compare-match
1
0
0
Output disabled
1
1
0
1
Initial
output
is 1
Output 0 on compare-match
Output 1 on compare-match
Toggle output on compare-match
1
0
0
0
TGR0C
Capture
Input capture on rising edge
1
is an
input source
Input capture on falling edge
input
is the
1
0
capture
TIOC0C pin
Input capture on both edges
1
register
1
0
0
1
1
0
1
Capture
input source
is channel 1/
count clock
Input capture
on TCNT1
count up/count down
Note: When the BFA bit of TMDR0 is set to 1 and TGR0C is being used as a buffer register, these
settings become ineffective and input capture/output compares do not occur.
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