SH7018 Datasheet, PDF (329/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

15.7.2 Port E Data Register (PFDR)
The port F data register (PFDR) is an 8-bit read-only register that stores port F data. The bits of
this register correspond to the various pins.
Writes to these bits are ignored, and do not affect the pin states. When these bits are read the pin
state, not the register value, is returned directly. However, 1 is returned while A/D converter
analog input is being sampled. Table 15.12 summarizes the port E data register read/write
operations.
PFDR is not initialized by a power-on reset, in standby mode, or in sleep mode. (The bits always
reflect the pin states.)
Bit:
7
6
5
4
3
2
PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR
Initial value:
*
*
*
*
*
*
R/W: R
R
R
R
R
R
Note: * These values depend on the pin state when the initial value is read.
1
PF1DR
*
R
0
PF0DR
*
R
Table 15.12 Port F Data Register (PFDR) Read/Write Operations
Pin Function Pin state
Input
General input
ANn
ANn: Analog input
Read
Pin state is read
1 is read
Write
Ignored (does not affect pin state)
Ignored (does not affect pin state)
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