SH7018 Datasheet, PDF (84/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bits 7 to 4, 1, and 0—IRQ0 to IRQ3, IRQ6, and IRQ7 Sense Select (IRQ0S to IRQ3S, IRQ6S,
IRQ7S): These bits set the IRQ0 to IRQ7 interrupt request detection mode.
Bits 7 to 4, 1, 0:
IRQ0S to IRQ3S,
IRQ6S, IRQ7S
0
1
Description
Interrupt request is detected on low level of IRQ input
Interrupt request is detected on falling edge of IRQ input
(Initial value)
• Bits 3 and 2—Reserved: These bits always read as 0. The write value should always be 0.
6.3.3 IRQ Status Register (ISR)
The ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input
pins IRQ0 to IRQ3, IRQ6, and IRQ7. When IRQ interrupts are set to edge detection, held interrupt
requests can be withdrawn by writing a 0 to IRQnF after reading an IRQnF = 1.
A power-on reset initializes ISR. It is not initialized in the standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
IRQ0F IRQ1F IRQ2F IRQ3F —
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W
R
2
1
0
— IRQ6F IRQ7F
0
0
0
R
R/W R/W
• Bits 15 to 8, 3, and 2—Reserved: These bits are always read as 0. The write value should
always be 0.
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