SH7018 Datasheet, PDF (187/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 9.1 8-Bit Timer 2 Registers
Name
Timer 2 control/status register
Timer 2 counter
Timer 2 constant register
Abbreviation R/W
T2CSR
R/W
T2CNT
R/W
T2COR
R/W
Initial
Value
H'0000
H'0000
H'0000
Address
H'FFFF862C
H'FFFF862E
H'FFFF8630
Access
Size
8, 16, 32
8, 16, 32
8, 16
9.2 Register Descriptions
9.2.1 Timer 2 Control/Status Register (T2CSR)
The timer 2 control/status register (T2CSR) is a 16-bit readable/writable* register that selects the
clock to be input to the timer 2 counter (T2CNT) and controls compare match interrupts (CMI).
T2CSR is initialized to H'0000 by a power-on reset.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
CMF CMIE CKS2 CKS1 CKS0
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W
R
R
• Bits 15 to 7—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 6—Compare Match Flag (CMF): Status flag that indicates a match between the values of
T2CNT and T2COR. The setting and clearing conditions for this flag are shown below.
Bit 6: CMF
Description
0
[Clearing condition]
Cleared by reading T2CSR when CMF = 1, then writing 0 in CMF (Initial value)
1
[Setting condition]
Set when T2CNT = T2COR*
Note: * When T2CNT and T2COR still contain their initial values (when the initial values have not
been changed or when the T2CNT value has not been incremented), CMF is not set even
though the T2CNT and T2COR values are the same (H'0000).
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