SH7018 Datasheet, PDF (88/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.4.2 Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
Address
4n–8
4n–4
4n
PC*¹
SR
32 bits
32 bits
SP*²
Notes: 1. PC: Start address of the next instruction (return destination instruction)
after the executing instruction
2. Always be certain that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
6.5 Interrupt Response Time
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is
accepted.
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