SH7018 Datasheet, PDF (370/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.8.2 Software Protection
Software protection can be implemented by setting the SWE bit in flash memory control register 1
(FLMCR1), the RAMS bit in erase block register 1 (EBR1), erase block register 2 (EBR2), and
RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in
flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase
mode. (See table 16.9.)
Table 16.9 Software Protection
Item
Description
SWE bit protection
• Clearing the SWE bit to 0 in FLMCR1 sets
the program/erase-protected state for all
blocks.
(Execute in on-chip RAM or external
memory.)
Block specification
protection
• Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2 (EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation protection •
Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
Functions
Program Erase
Yes
Yes
—
Yes
Yes
Yes
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