SH7018 Datasheet, PDF (262/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Note: An overrun error occurs only during the receive operation, and the sync clock is output
until the RE bit is cleared to 0. When you want to perform a receive operation in one-
character units, select external clock for the clock source.
SCI1 Initialization (Clock Synchronous Mode): Before transmitting or receiving, software must
clear the TE and RE bits to 0 in the serial control register (SCR1), then initialize the SCI1 as
follows.
When changing the mode or communication format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR1). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR1), which retain their previous contents.
Figure 12.15 is a sample flowchart for initializing the SCI1.
1. Select the clock source in the serial control register (SCR1). Leave RIE, TIE, TEIE, MPIE, TE,
and RE cleared to 0.
2. Select the communication format in the serial mode register (SMR1).
3. Write the value corresponding to the bit rate in the bit rate register (BRR1) unless an external
clock is used.
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
serial control register (SCR1) to 1. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD pins
becomes usable in response to the PFC corresponding bits and the TE, RE bit settings.
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