SH7018 Datasheet, PDF (220/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
12.2.3 Transmit Shift Register (TSR1)
The transmit shift register (TSR1) transmits serial data. The SCI1 loads transmit data from the
transmit data register (TDR1) into the TSR1, then transmits the data serially from the TxD pin,
LSB (bit 0) first. After transmitting one data byte, the SCI1 automatically loads the next transmit
data from the TDR1 into the TSR1 and starts transmitting again. If the TDRE bit of the SSR1 is 1,
however, the SCI1 does not load the TDR1 contents into the TSR1.
The CPU cannot read or write the TSR1 directly.
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
12.2.4 Transmit Data Register (TDR1)
The transmit data register (TDR1) is an 8-bit register that stores data for serial transmission. When
the SCI1 detects that the transmit shift register (TSR1) is empty, it moves transmit data written in
the TDR1 into the TSR1 and starts serial transmission. Continuous serial transmission is possible
by writing the next transmit data in the TDR1 during serial transmission from the TSR1.
The CPU can always read and write the TDR1. The TDR1 is initialized to H'FF by a power-on
reset or in standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.2.5 Serial Mode Register (SMR1)
The serial mode register (SMR1) is an 8-bit register that specifies the SCI1 serial communication
format and selects the clock source for the baud rate generator.
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