SH7018 Datasheet, PDF (271/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

12.4 Interrupt
The SCI1 has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full
(RxI), and transmit-data-empty (TxI). Table 12.12 lists the interrupt sources and indicates their
priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial
control register (SCR1). Each interrupt request is sent separately to the interrupt controller.
TxI is requested when the TDRE bit in the serial status register (SSR1) is set to 1.
RxI is requested when the RDRF bit in the SSR1 is set to 1.
ERI is requested when the ORER, FER, or PER bit in the SSR1 is set to 1.
TEI is requested when the TEND bit in the SSR1 is set to 1.
Where the TxI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates
that the transmit operation has ended.
Table 12.12 SCI1 Interrupt Sources
Interrupt Source
ERI
RxI
TxI
TEI
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Priority
High
Low
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