SH7018 Datasheet, PDF (226/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 1: Bit 0:
CKE1 CKE0 Description^*1
0
0
Asynchronous mode
Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)*²
Clock synchronous mode
Internal clock, SCK pin used for synchronous clock
output*²
0
1
Asynchronous mode
Internal clock, SCK pin used for clock output*³
Clock synchronous mode
Internal clock, SCK pin used for synchronous clock
output
1
0
Asynchronous mode
External clock, SCK pin used for clock input*⁴
Clock synchronous mode
External clock, SCK pin used for synchronous clock
input
1
1
Asynchronous mode
External clock, SCK pin used for clock input*⁴
Clock synchronous mode
External clock, SCK pin used for synchronous clock
input
Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to
select the SCK function for this pin, as well as the I/O direction.
2. Initial value.
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
12.2.7 Serial Status Register (SSR1)
The serial status register (SSR1) is an 8-bit register containing multiprocessor bit values, and
status flags that indicate SCI1 operating status.
The CPU can always read and write the SSR1, but cannot write 1 in the status flags (TDRE,
RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read
(after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The
SSR1 is initialized to H'84 by a power-on reset or in standby mode.
Bit: 7
6
5
4
3
TDRE RDRF ORER FER PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * The only value that can be written is a 0 to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
• Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI1 has loaded transmit
data from the TDR1 into the TSR1 and new serial transmit data can be written in the TDR1.
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