SH7018 Datasheet, PDF (53/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.17 System Control Instructions (cont)
Instruction
Instruction Code
Operation
Exec.
Cycles T Bit
STS.L MACH,@–Rn 0100nnnn00000010
Rn–4 → Rn, MACH → (Rn) 1
—
STS.L MACL,@–Rn 0100nnnn00010010
Rn–4 → Rn, MACL → (Rn) 1
—
STS.L PR,@–Rn
0100nnnn00100010
Rn–4 → Rn, PR → (Rn)
1
—
TRAPA #imm
11000011iiiiiiii
PC/SR → stack area, (imm) 8
—
→ PC
Note: * The number of execution cycles before the chip enters sleep mode: The execution cycles
shown in the table are minimums. The actual number of cycles may be increased when (1)
contention occurs between instruction fetches and data access, or (2) when the destination
register of the load instruction (memory → register) and the register used by the next
instruction are the same.
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