SH7018 Datasheet, PDF (265/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Figure 12.17 shows an example of SCI1 transmit operation.
Transmit direction
Synchroni-
zation clock
Serial data
LSB
Bit 0 Bit 1
MSB
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
TDRE
TEND
TxI
request
TxI interrupt
handler writes
data in TDR1 and
clears TDRE to 0
TxI
request
1 frame
TEI
request
Figure 12.17 Example of SCI1 Transmit Operation
SCI1 serial transmission operates as follows.
1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0 the SCI1
recognizes that the transmit data register (TDR1) contains new data and loads this data from
the TDR1 into the transmit shift register (TSR1).
2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR1 is set to 1,
the SCI1 requests a transmit-data-empty interrupt (TxI) at this time.
If clock output mode is selected, the SCI1 outputs eight synchronous clock pulses. If an
external clock source is selected, the SCI1 outputs data in synchronization with the input clock.
Data are output from the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI1 checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI1 loads
data from the TDR1 into the TSR1, then begins serial transmission of the next frame. If TDRE
is 1, the SCI1 sets the TEND bit in the SSR1 to 1, transmits the MSB, then holds the transmit
data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in the SCR1 is
set to 1, a transmit-end interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK pin is held in the high state.
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