SH7018 Datasheet, PDF (86/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.4 Interrupt Operation
6.4.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
following the priority levels set in interrupt priority level setting registers A to H (IPRA to
IPRH). Lower-priority interrupts are ignored*. If a number of interrupts with the same priority
level occur, or if multiple interrupts occur within a single module, the interrupt with the highest
default priority or the highest priority within its IPR setting range (as indicated in table 6.3) is
selected.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3 to I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3 to I0, the request is ignored. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. The interrupt controller detects the interrupt request sent from the interrupt controller when it
decodes the next instruction to be executed. Instead of executing the decoded instruction, the
CPU starts interrupt exception processing (figure 6.5).
5. The status register (SR) and program counter (PC) are saved onto the stack.
6. The priority level of the accepted interrupt is written to bits I3 to I0 in SR.
7. The CPU reads the start address of the exception service routine from the exception vector
table for the accepted interrupt, jumps to that address, and starts executing the program there.
This jump is not a delay branch.
Note:
An interrupt request for which edge detection has been set is held pending until it is
accepted. However, an IRQ interrupt can be cleared by an IRQ status register (ISR)
access. For details see section 6.2.2, IRQ Interrupts.
Pending edge-detected interrupts are cleared by a power-on reset.
70