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SH7018 Datasheet, PDF (163/431 Pages) Renesas Technology Corp – SuperH™ RISC engine | |||
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Setting TGF Flag Timing during Input Capture: Figure 8.36 shows timing for the TGF flag of
the timer status register (TSR) due to input capture, as well as TGI interrupt request signal timing.
Ï
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 8.36 TGI Interrupt Timing (Input Capture)
Setting Timing for Overflow Flag (TCFV): Figure 8.37 shows timing for the TCFV flag of the
timer status register (TSR) due to overflow, as well as TCIV interrupt request signal timing.
Ï
TCNT
input clock
TCNT
(overflow)
Overflow
signal
TCFV flag
H'FFFF
H'0000
TCIV interrupt
Figure 8.37 TCIV Interrupt Setting Timing
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