SH7018 Datasheet, PDF (343/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection). FLMCR2 is initialized to H'00 by a power-on reset.
When on-chip flash memory is disabled, a read will return H'00.
Bit: 7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
• Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the
error-protection state.
Bit 7:
FLER
0
1
Description
Flash memory is operating normally.
Flash memory program/erase protection (error protection) is disabled.
[Clearing condition]
Power-on reset
An error has occurred during flash memory programming/erasing.
Flash memory program/erase protection (error protection) is enabled.
[Setting condition]
See section 16.8.3, Error Protection.
(Initial value)
• Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
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