SH7018 Datasheet, PDF (117/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 8.3 Register Configuration (cont)
Chan-
nel Name
Abbrevi-
ation R/W
Initial
Value
Address
2
Timer control register 2
TCR2 R/W H'00
H'FFFF82A0
Timer mode register 2
TMDR2 R/W H'C0
H'FFFF82A1
Timer I/O control register 2 TIOR2 R/W H'00
H'FFFF82A2
Timer interrupt enable
register 2
TIER2 R/W H'40
H'FFFF82A4
Timer status register 2
TSR2 R/(W)*² H'C0
H'FFFF82A5
Timer counter 2
TCNT2 R/W H'0000 H'FFFF82A6
General register 2A
TGR2A R/W H'FFFF H'FFFF82A8
General register 2B
TGR2B R/W H'FFFF H'FFFF82AA
Notes: Do not access empty addresses.
1. 16-bit registers (TCNT, TGR) cannot be read or written in 8-bit units.
2. Write 0 to clear flags.
Access Size
(Bits)*¹
8, 16
8
8, 16, 32
16, 32
8.2 MTU Register Descriptions
8.2.1 Timer Control Register (TCR)
The TCR is an 8-bit read/write register for controlling the TCNT counter for each channel. The
MTU has three TCR registers, one for each of the channels 0 to 2. TCR is initialized to H'00 by a
power-on reset or the standby mode.
Channel 0: TCR0
Bit: 7
6
5
4
3
2
1
0
CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Channels 1 and 2: TCR1, TCR2
Bit: 7
6
5
4
3
2
1
0
— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
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