SH7018 Datasheet, PDF (257/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.
1. SCI1 initialization: Set the RxD pin using the PFC.
2. ID receive cycle: Set the MPIE bit in the serial control register (SCR1) to 1.
3. SCI1 status check and compare to ID reception: Read the serial status register (SSR1), check
that RDRF is set to 1, then read data from the receive data register (RDR1) and compare with
the processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and
clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
bits in SSR1 to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
5. SCI1 status check and data receiving: Read SSR1, check that RDRF is set to 1, then read data
from the receive data register (RDR1).
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