SH7018 Datasheet, PDF (248/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

In transmitting serial data, the SCI1 operates as follows:
1. The SCI1 monitors the TDRE bit in the SSR1. When TDRE is cleared to 0, the SCI1
recognizes that the transmit data register (TDR1) contains new data, and loads this data from
the TDR1 into the transmit shift register (TSR1).
2. After loading the data from the TDR1 into the TSR1, the SCI1 sets the TDRE bit to 1 and
starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR1,
the SCI1 requests a transmit-data-empty interrupt (TxI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Marking: output of 1 bits continues until the start bit of the next transmit data.
3. The SCI1 checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI1 loads new
data from the TDR1 into the TSR1, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI1 sets the TEND bit to 1 in the SSR1, outputs the stop bit,
then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the
SCR1 is set to 1, a transmit-end interrupt (TEI) is requested.
Figure 12.6 shows an example of SCI transmit operation in asynchronous mode.
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