SH7018 Datasheet, PDF (156/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.5 Interrupts
8.5.1 Interrupt Sources and Priority Ranking
The MTU has two interrupt sources: TGR register compare-match/input captures, TCNT counter
overflows. Because each of these three types of interrupts are allocated its own dedicated status
flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be
independently enabled or disabled.
When an interrupt source is generated, the corresponding status flag in the timer status register
(TSR) is set to 1. If the corresponding enable/disable bit in the timer input enable register (TIER)
is set to 1 at this time, the MTU makes an interrupt request of the interrupt controller. The
interrupt request is canceled by clearing the status flag to 0.
The channel priority order can be changed with the interrupt controller. The priority ranking
within a channel is fixed. For more information, see section 6, Interrupt Controller.
Table 8.8 lists the MTU interrupt sources.
Input Capture/Compare Match Interrupts: If the TGIE bit of the timer input enable register
(TIER) is already set to 1 when the TGF flag in the timer status register (TSR) is set to 1 by a TGR
register input capture/compare-match of any channel, an interrupt request is sent to the interrupt
controller. The interrupt request is canceled by clearing the TGF flag to 0. The MTU has 8 input
capture/compare-match interrupts; four each for channel 0, and two each for channels 1 and 2.
Overflow Interrupts: If the TCIEV bit of the TIER is already set to 1 when the TCFV flag in the
TSR is set to 1 by a TCNT counter overflow of any channel, an interrupt request is sent to the
interrupt controller. The interrupt request is canceled by clearing the TCFV flag to 0. The MTU
has three overflow interrupts, one for each channel.
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