SH7018 Datasheet, PDF (49/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.13 Arithmetic Operation Instructions (cont)
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow
Borrow → T
SUBV Rm,Rn
0011nnnnmmmm1011
Rn–Rm → Rn,
Underflow → T
1
Overflow
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Instruction
AND Rm,Rn
AND #imm,R0
AND.B #imm,@(R0,GBR)
Instruction Code
0010nnnnmmmm1001
11001001iiiiiiii
11001101iiiiiiii
NOT
OR
OR
OR.B
Rm,Rn
Rm,Rn
#imm,R0
#imm,@(R0,GBR)
0110nnnnmmmm0111
0010nnnnmmmm1011
11001011iiiiiiii
11001111iiiiiiii
TAS.B @Rn
0100nnnn00011011
TST Rm,Rn
0010nnnnmmmm1000
TST #imm,R0
11001000iiiiiiii
TST.B #imm,@(R0,GBR) 11001100iiiiiiii
XOR Rm,Rn
XOR #imm,R0
XOR.B #imm,@(R0,GBR)
0010nnnnmmmm1010
11001010iiiiiiii
11001110iiiiiiii
Operation
Execu-
tion
Cycles T Bit
Rn & Rm → Rn
1
—
R0 & imm → R0
1
—
(R0 + GBR) & imm → 3
—
(R0 + GBR)
~Rm → Rn
1
—
Rn | Rm → Rn
1
—
R0 | imm → R0
1
—
(R0 + GBR) | imm →
3
—
(R0 + GBR)
If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)
Test
result
Rn & Rm; if the result is 1
0, 1 → T
Test
result
R0 & imm; if the result is 1
0, 1 → T
Test
result
(R0 + GBR) & imm; if 3
the result is 0, 1 → T
Test
result
Rn ^ Rm → Rn
1
—
R0 ^ imm → R0
1
—
(R0 + GBR) ^ imm → 3
—
(R0 + GBR)
33