SH7018 Datasheet, PDF (100/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 7 (CW3)
0
1
Description
No CS3 space continuous access idle cycles
One CS3 space continuous access idle cycle
(Initial value)
Bit 6 (CW2)
0
1
Description
No CS2 space continuous access idle cycles
One CS2 space continuous access idle cycle
(Initial value)
Bit 5 (CW1)
0
1
Description
No CS1 space continuous access idle cycles
One CS1 space continuous access idle cycle
(Initial value)
Bit 4 (CW0)
0
1
Description
No CS0 space continuous access idle cycles
One CS0 space continuous access idle cycle
(Initial value)
• Bits 3 to 0—CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle
extension specification is for making insertions to prevent extension of the RD signal or WRL
signal assert period beyond the length of the CSn signal assert period. Extended cycles insert
one cycle before and after each bus cycle, which simplifies interfaces with external devices and
also has the effect of extending write data hold time. Refer to section 7.3.3, CS Assert Period
Extension, for details.
SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert
extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access
and SW0 specifies the CS assert extension for CS0 space access.
Bit 3 (SW3)
0
1
Description
No CS3 space CS assert extension
CS3 space CS assert extension
(Initial value)
Bit 2 (SW2)
0
1
Description
No CS2 space CS assert extension
CS2 space CS assert extension
(Initial value)
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