SH7018 Datasheet, PDF (345/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 16.3 Flash Memory Erase Blocks
Block (Size)
EB0 (4 kB)
EB1 (4 kB)
EB2 (4 kB)
EB3 (4 kB)
EB4 (4 kB)
EB5 (4 kB)
EB6 (4 kB)
EB7 (4 kB)
EB8 (32 kB)
EB9 (64 kB)
EB10 (32 kB)
Address
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
H'008000 to H'00FFFF
H'010000 to H'01FFFF
H'020000 to H'027FFF
16.5.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a power-on reset. It is
not initialized in standby mode. RAMER settings should be made in user mode or user program
mode.
Flash memory area divisions are shown in table 16.4. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— RAMS RAM1 RAM0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
• Bits 15 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
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