SH7018 Datasheet, PDF (416/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

(1)
CK
Address
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
(1): Write cycle of ADCSR
(2): Address of ADCSR
t_D: A/D conversion start delay time
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 19.13 Analog Conversion Timing
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