SH7018 Datasheet, PDF (207/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.1.3 Register Configuration
Table 11.1 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 11.1 WDT Registers
Address
Name
Abbreviation R/W
Initial Value Write*¹
Read*²
Timer control/status TCSR
register
R/(W)*³ H'18
H'FFFF8610 H'FFFF8610
Timer counter
TCNT
R/W
H'00
H'FFFF8611
Reset control/status RSTCSR
register
R/(W)*³ H'1F
H'FFFF8612 H'FFFF8613
Notes: 1. Write by word transfer. It cannot be written in byte or longword.
2. Read by byte transfer. It cannot be read in word or longword.
3. Only 0 can be written in bit 7 to clear the flag.
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is
more difficult to write to. See section 11.2.4, Register Access, for details.) When the timer enable
bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts
counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the
TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), an internal reset
signal from the watchdog timer* or interval timer interrupt (ITI) is generated, depending on the
mode selected in the WT/IT bit of the TCSR.
The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not
initialized in the standby mode.
Note: * If RSTE of RSTCSR is set to 1.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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