SH7018 Datasheet, PDF (221/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

The CPU can always read and write the SMR1. The SMR1 is initialized to H'00 by a power-on
reset.
Bit: 7
C/A
Initial value: 0
R/W: R/W
6
5
CHR
PE
0
0
R/W R/W
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
• Bit 7—Communication Mode (C/A): Sets the SCI operation mode to either start-stop
synchronous mode or clock synchronous mode.
Bit 7: C/A
0
1
Description
Start-stop synchronous mode
Clock synchronous mode
(Initial value)
• Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. The
number of data bits is fixed at eight in the clock synchronous mode, regardless of the CHR
setting.
Bit 6: CHR
0
1
Description
Eight-bit data
(Initial value)
Seven-bit data
When 7-bit data is selected, the MSB (bit 7) of the transmit data register
is not transmitted.
• Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data. A parity bit is added in the clock synchronous mode regardless of the
setting of the PE bit, and no checking is performed.
Bit 5: PE
0
1
Description
Parity bit not added or checked
(Initial value)
Parity bit added and checked
When PE is set to 1, an even or odd parity bit is added to transmit data,
depending on the parity mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode setting.
• Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only when the parity enable bit (PE) is set to 1 to enable parity addition
and check. The O/E setting is ignored when parity addition and check is disabled.
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