SH7018 Datasheet, PDF (79/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.2.3 On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules:
• Multifunction timer pulse unit (MTU)
• Compare match timer (CMT)
• Serial communications interface (SCI1)
• A/D converter (A/D)
• Watchdog timer (WDT)
• 8-bit timer 2 (TIM2)
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers C to H (IPRC to
IPRH).
On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3 to
I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt
that was accepted.
6.2.4 Interrupt Exception Vectors and Priority Rankings
Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. See section 5 Exception Processing, table 5.4, Calculating Exception
Processing Vector Table Addresses.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A to H (IPRA to IPRH). The
ranking of interrupt sources for IPRC to IPRH, however, must be the order listed under Priority
Order Within IPR Setting Range in table 6.3 and cannot be changed. A power-on reset assigns
priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority
level is assigned to two or more interrupt sources and interrupts from those sources occur
simultaneously, their priority order is the default priority order indicated at the right in table 6.3.
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