SH7018 Datasheet, PDF (94/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.1.5 Address Map
Figure 7.2 shows the address format used by this LSI.
A31
A24 A23, A22 A21
A0
Output address:
Output from the address pins
CS space selection:
Decoded, outputs CS0 to CS3 when A31 to A24 = 00000000
Space selection:
Not output externally; used to select the type of space
On-chip ROM space or CS space when 00000000 (H'00)
Reserved (do not access) when 00000001 to 11111110 (H'01 to H'FE)
On-chip peripheral module space or on-chip RAM space when 11111111 (H'FF)
Figure 7.2 Address Format
This LSI uses 32-bit addresses:
• A31 to A24 are used to select the type of space and are not output externally.
• Bits A23 and A22 are decoded and output as chip select signals (CS0 to CS3) for the
corresponding areas when bits A31 to A24 are 00000000.
• A21 to A0 are output externally.
Table 7.3 shows an address map.
78