SH7018 Datasheet, PDF (353/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.7.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
After the elapse of a given programming time, the programming mode is exited (the P bit in
FLMCR1 is cleared, then the PSUn bit is cleared at least 5 µs later). The watchdog timer is cleared
after the elapse of 5 µs or more, and the operating mode is switched to program-verify mode by
setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF
data should be made to the addresses to be read. The dummy write should be executed after the
elapse of 4 µs or more. When the flash memory is read in this state (verify data is read in 32-bit
units), the data at the latched address is read. Wait at least 2 µs after the dummy write before
performing this read operation. Next, the written data is compared with the verify data, and
reprogram data is computed (see figure 16.12) and transferred to the reprogram data area. After
128 bytes of data have been verified, exit program verify mode, wait for at least 2 µs, clear the
SWE bit in FLMCR1, then wait for at least 100 µs. If reprogramming is necessary, set program
mode again, and repeat the program/program-verify sequence as before. However, ensure that the
program/program-verify sequence is not repeated more than 1,000 times on the same bits.
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