SH7018 Datasheet, PDF (230/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

12.2.8 Bit Rate Register (BRR1)
The bit rate register (BRR1) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR1), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR1. The BRR1 is initialized to H'FF by a power-on
reset.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 12.3 lists examples of BRR1 settings in the asynchronous mode. Table 12.4 lists examples
of BRR1 settings in the clock synchronous mode.
Table 12.3 Bit Rates and BRR1 Settings (Asynchronous Mode)
Bit Rate
(Bits/s)
110
150
300
600
1200
2400
4800
9600
14400
19200
28800
31250
38400
4
n N Error (%)
2 70 0.03
1 207 0.16
1 103 0.16
0 207 0.16
0 103 0.16
0 51 0.16
0 25 0.16
0 12 0.16
0 8 –3.55
0 6 –6.99
0 3 8.51
0 3 0.00
0 2 8.51
φ (MHz)
4.9152
n N Error (%)
2 86 0.31
1 255 0.00
1 127 0.00
0 255 0.00
0 127 0.00
0 63 0.00
0 31 0.00
0 15 0.00
0 10 –3.03
0 7 0.00
0 4 6.67
0 4 –1.70
0 3 0.00
6
n N Error (%)
2 106 –0.44
2 77 0.16
1 155 0.16
1 77 0.16
0 155 0.16
0 77 0.16
0 38 0.16
0 19 –2.34
0 12 0.16
0 9 –2.34
0 6 –6.99
0 5 0.00
0 4 –2.34
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