SH7018 Datasheet, PDF (168/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Contention between TGR Write and Input Capture: If an input capture signal is issued in the
T₂ state of the TGR read cycle, input capture has priority, and TGR write does not occur (figure
8.43).
TGR write cycle
T₁
T₂
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
TGR
M
Figure 8.43 TGR Write and Input Capture Contention
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