SH7018 Datasheet, PDF (369/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
16.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), erase block register 1 (EBR1), and erase block register 2 (EBR2). The FLMCR1,
EBR1, and EBR2 settings are retained in the error-protected state. (See table 16.8.)
Table 16.8 Hardware Protection
Item
FWP pin protection
Reset/standby
protection
Functions
Description
Program Erase
• When a high level is input to the FWP pin, Yes
Yes
FLMCR1, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
• In a reset (including a WDT overflow reset) Yes
Yes
and in standby mode, FLMCR1, EBR1,
and EBR2 are initialized, and the
program/erase-protected state is entered.
• In a power-on reset via the RES pin, the
reset state is not entered unless the RES
pin is held low until oscillation stabilizes
after powering on. In the case of a reset
during operation, hold the RES pin low for
the RES pulse width specified in the AC
Characteristics section.
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