SH7018 Datasheet, PDF (54/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

2.5 Processing States
2.5.1 State Transitions
The CPU has for processing states: reset, exception processing, program execution, and power-
down. Figure 2.6 shows the transitions between the states.
From all states
when RES= 0
Power-on
reset state
Interrupt triggered
Reset state
RES= 1
Exception processing state
Exception
processing
triggered
Exception
processing
ends
NMI interrupt
triggered
Sleep instruction
when SBY bit
cleared
Program execution state
Sleep instruction
when SBY bit
set
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States
Reset State: The CPU resets in this state. When the RES pin goes low, a power-on reset results.
Exception Processing State: This is a transient state that occurs when the CPU’s processing state
flow is altered due to the triggering of exception processing.
In the case of a reset, the execution start address and stack pointer (SP) initial value are fetched
from the exception processing vector table as the initial values of the program counter (PC) and
stored. The CPU then branches to the execution start address and execution of the program begins.
38