SH7018 Datasheet, PDF (104/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.3 Accessing Ordinary Space
A strobe signal is output by ordinary space accesses to provide primarily for SRAM or ROM
direct connections.
7.3.1 Basic Timing
Figure 7.3 shows the basic timing of ordinary space accesses. Ordinary access bus cycles are
performed in 2 states.
T₁
T₂
CK
Address
CSn
Read
RD
Data
Write
WRL
Data
Figure 7.3 Basic Timing of Ordinary Space Access
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) are fetched by the LSI on RD, using the required byte locations.
During a write, the following signals are associated with transfer of these actual byte locations:
WRL (bits 7 to 0).
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