SH7018 Datasheet, PDF (166/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Contention between Buffer Register Write and Compare Match: If a compare-match occurs in
the T₂ state of the TGR write cycle, data is transferred by the buffer operation from the buffer
register to the TGR. On channel 0, the data to be transferred is that after the write (figure 8.41).
TGR write cycle
T₁
T₂
φ
Address
Write signal
Compare
match
signal
Compare
match buffer
signal
Buffer
register
TGR
Buffer register
address
Buffer register write data
N
M
M
Figure 8.41 TGR Write and Compare-Match Contention (Channel 0)
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