SH7018 Datasheet, PDF (18/431 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.1 Features
Item
CPU
Specification
• Original Hitachi architecture
• Internal 32-bit configuration
• General register machine
 General registers: 32-bit × 16
 Control registers: 32-bit × 3
 System registers: 32-bit × 4
• RISC (reduced instruction set computer) instruction set
 Instruction length: 16-bit fixed for efficient coding
 Load-store architecture (basic operations executed between
registers)
 Extended branching instructions to minimize pipeline disturbance
when branching
 Instruction set based on C language
• Instruction execution time of one cycle per instruction (50 ns per
instruction when operating at 20 MHz)
• Maximum address space of 4 GB supported by architecture
• On-chip multiplier
The on-chip multiplier handles 32 × 32 → 64 multiplication
operations in two to four cycles and 32 × 32 + 64 → 64
multiplication/accumulation operations in two to four cycles.
• Pipeline
5-stage pipeline
Interrupt controller (INTC) • Seven external interrupt pins (NMI, IRQ0 to IRQ3, IRQ6, IRQ7)
• 16-level priority setting supported
Bus state controller (BSC) •
•
•
•
Bus access to external memory and external devices supported
 8-bit fixed external data bus
Address space divided into four areas (SRAM space × 4 areas)
Wait cycles may be specified (0 to 3 cycles) separately for each
area.
Chip select signals corresponding to memory areas are output.
Wait cycles may be inserted using external WAIT signal.
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